AS4C4M16SA-6TCNTR, DRAM SDR, 64Mb, 4M x 16, 3.3V, 54pin TSOP II, 166 MHz, Commercial Temp(A) tape and reel

AS4C SDRAM Alliance Memory AS4C SDRAM is high-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.