AS4C64M16D2A-25BCN, DRAM DDR2, 1G, 64M x 16, 1.8V, 96-ball BGA, 400 MHz, (A-die), Commercial Temp - Tray

DDR2 SDRAM Alliance Memory DDR2 SDRAM is designed to comply with DDR2 SDRAM key features. Features such as posted CAS# with additive latency, Write latency=Read latency -1, and On-Die Termination (ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style.